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19-1319; Rev 3; 7/08
KIT ATION EVALU ABLE AVAIL
2x4-Channel, Simultaneous-Sampling 14-Bit DAS
General Description Features
Four Simultaneous-Sampling T/H Amplifiers with Two Multiplexed Inputs (eight single-ended inputs total) 3s Conversion Time per Channel Throughput: 250ksps (1 channel) 142ksps (2 channels) 100ksps (3 channels) 76ksps (4 channels) Input Range: 5V (MAX125) 2.5V (MAX126) Fault-Protected Input Multiplexer (17V) 5V Supplies Internal +2.5V or External Reference Operation Programmable On-Board Sequencer High-Speed Parallel DSP Interface
MAX125/MAX126
The MAX125/MAX126 are high-speed, multichannel, 14-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 14-bit, 3s, successive-approximation analog-to-digital converter (ADC), a +2.5V reference, a buffered reference input, and a bank of four simultaneous-sampling T/H amplifiers that preserve the relative phase information of the sampled inputs. The MAX125/MAX126 have two multiplexed inputs for each T/H, allowing a total of eight inputs. In addition, the converter is overvoltage tolerant to 17V; a fault condition on any channel will not harm the IC. Available input ranges are 5V (MAX125) and 2.5V (MAX126). An on-board sequencer converts one to four channels per CONVST pulse. In the default mode, one T/H output (CH1A) is converted. An interrupt signal (INT) is provided after the last conversion is complete. Convert two, three, or four channels by reprogramming the MAX125/MAX126 through the bidirectional parallel interface. Once programmed, the MAX125/MAX126 continue to convert the specified number of channels per CONVST pulse until they are reprogrammed. The channels are converted sequentially, beginning with CH1. The INT signal always follows the end of the last conversion in a conversion sequence. The ADC converts each assigned channel in 3s and stores the result in an internal 14x4 RAM. Upon completion of the conversions, data can be accessed by applying successive pulses to the RD pin. Four successive reads access four data words sequentially. The parallel interface's data-access and bus-release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microprocessors, so the MAX125/MAX126 conversion results can be accessed without resorting to wait states.
Ordering Information
PART MAX125CCAX MAX125CEAX MAX126CCAX MAX126CEAX TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 36 SSOP 36 SSOP 36 SSOP 36 SSOP INL (LSB) 4 4 4 4
Applications
Multiphase Motor Control Power-Grid Synchronization Power-Factor Monitoring Digital Signal Processing Vibration and Waveform Analysis
Typical Operating Circuit appears at end of data sheet. Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ...........................................................-0.3V to 6V AVSS to AGND ............................................................0.3V to -6V DVDD to DGND ...........................................................-0.3V to 6V AGND to DGND .......................................................-0.3V to 0.3V CH_ _ to AGND....................................................................17V REFIN, REFOUT to AGND ..........................................-0.3V to 6V Digital Inputs/Outputs to DGND ..............-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) SSOP (derate 11.8mW/C above +70C) ....................941mW Operating Temperature Ranges MAX125CCAX/MAX126CCAX ............................0C to +70C MAX125CEAX/MAX126CEAX ..........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec)................................300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V 5%, AVSS = -5V 5%, DVDD = +5V 5%, VREFIN = 2.5V, AGND = DGND = 0V, 4.7F capacitor from REFOUT to AGND, 0.1F capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER DC ACCURACY (Note 1) Resolution Integral Nonlinearity No Missing Codes Bipolar Zero Error Bipolar Zero-Error Match Zero-Code Tempco Gain Error Gain-Error Match Gain-Error Tempco DYNAMIC PERFORMANCE (fCLK = 16MHz, fIN = 10.06kHz (Notes 1, 3) Single-channel mode, MAX125 Signal-to-Noise Plus Distortion SINAD channel 1A, 250ksps (Note MAX126 4) Single-channel mode, channel 1A, Total Harmonic Distortion THD 250ksps (Notes 4, 5) Spurious-Free Dynamic Range Channel-to-Channel Isolation SFDR Single-channel mode, channel 1A, 250ksps (Note 4) Single-channel mode, channel 1A, 250ksps (Note 6) 72 70 TA = +25C TA = TMIN to TMAX Between all channels 1.2 5 75 72 -89 80 90 80 -80 TA = +25C TA = TMIN to TMAX Between all channels 1.2 5 5 10 15 5 N INL All channels (Note 2) 13 5 15 25 5 14 2 4 Bits LSB Bits mV mV ppm/C mV mV ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
dB dB dB dB
2
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V 5%, AVSS = -5V 5%, DVDD = +5V 5%, VREFIN = 2.5V, AGND = DGND = 0V, 4.7F capacitor from REFOUT to AGND, 0.1F capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Input Voltage Range Input Current Input Capacitance TRACK/HOLD Acquisition Time Small-Signal Bandwidth Full-Power Bandwidth Droop Rate Aperture Delay Aperture Jitter Aperture-Delay Matching REFERENCE OUTPUT (Note 8) Output Voltage External Load Regulation REFOUT Tempco External Capacitive Bypass at REFIN External Capacitive Bypass at REFOUT REFERENCE INPUT Input Voltage Range Input Current Input Resistance Input Capacitance EXTERNAL CLOCK External Clock Frequency DIGITAL INPUTS (CONVST, RD, WR, CS, CLK, A0-A3) (Note 1) Input High Voltage Input Low Voltage Input Current Input Capacitance VIH VIL IIN CIN CONVST, RD, WR, CS, CLK A0-A3 (Note 7) 2.4 0.8 1 10 15 V V A pF 0.1 16 MHz REFIN = 2.5V (Note 10) (Note 7) 10 10 2.50 10% 10 V A k pF VREFOUT TA = +25C 0mA < ILOAD < 1mA (Note 9) 0.1 4.7 22 2.475 2.500 1 30 2.525 V % ppm/C F F tACQ 1 8 0.5 2 5 30 500 s MHz MHz mV/ms ns psRMS ps VIN IIN CIN MAX125 MAX126 MAX125, VIN = 5V MAX126, VIN = 2.5V (Note 7) 5 2.5 667 16 V A A pF
MAX125/MAX126
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V 5%, AVSS = -5V 5%, DVDD = +5V 5%, VREFIN = 2.5V, AGND = DGND = 0V, 4.7F capacitor from REFOUT to AGND, 0.1F capacitor from REFIN to AGND, fCLK = 16MHz, external clock, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage Digital Supply Voltage Positive Supply Current Negative Supply Current Digital Supply Current Shutdown Positive Current Shutdown Negative Current Shutdown Digital Current Positive Supply Rejection Negative Supply Rejection Power Dissipation PSRR+ PSRR(Note 11) (Note 11) (Note 12) 165 1 -1 3 2 2 250 AVDD AVSS DVDD I(AVDD) I(AVSS) I(DVDD) -17 4.75 -5.25 4.75 5 -5 5 17 -13 3 5 3 5.25 -4.75 5.25 25 V V V mA mA mA mA mA mA LSB LSB mW SYMBOL VOH VOL IOUT = 1mA IOUT = -1.6mA D0-D13 (Note 7) CONDITIONS MIN 4 0.4 10 10 TYP MAX UNITS V V A pF DIGITAL OUTPUTS (D0-D13, INT) (Note 1)
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS
TIMING CHARACTERISTICS (Figure 4)
(AVDD = +5V, AVSS = -5V, DVDD = +5V, AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONVST Pulse Width CS to WR Setup Time CS to WR Hold Time WR Low Pulse Width CS to CONVST Delay Address Setup Time Address Hold Time RD to INT Delay Delay Time Between Reads CS to RD Setup Time CS to RD Hold Time RD Low Pulse Width Data-Access Time Bus-Relinquish Time SYMBOL tCW tCWS tCWH tWR tCSD tAS tAH tID tRD tCRS tCRH tRD tDA tDH 25pF load (Note 13) 25pF load (Note 14) Mode 1, 1 channel Conversion Time tCONV Mode 2, 2 channel Mode 3, 3 channel Mode 4, 4 channel Mode 1, 1 channel Conversion Rate/Channel Mode 2, 2 channel Mode 3, 3 channel Mode 4, 4 channel Start-Up Time Exiting shutdown 5 5 25pF load 40 0 0 30 30 45 3 6 9 12 250 142 100 76 s ksps s CONDITIONS MIN 30 0 0 30 125 30 0 30 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX125/MAX126
Note 1: AVDD = +5V, AVSS = -5V, DVDD = +5V, VREFIN = 2.500V (external), VIN = 5V (MAX125) or 2.5V (MAX126). Note 2: Relative accuracy is the analog value's deviation at any code from its theoretical value after the full-scale range has been calibrated. Note 3: CLK synchronized with CONVST. Note 4: fIN = 10.06kHz, VIN = 5V (MAX125) or 2.5V (MAX126). Note 5: First five harmonics. Note 6: All inputs except CH1A driven with 5V (MAX125) or 2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized. Note 7: Guaranteed by design. Not production tested. Note 8: AVDD = +5V, AVSS = -5V, DVDD = +5V, VIN = 0V (all channels). Note 9: Temperature drift is defined as the change in output voltage from +25C to TMIN or TMAX. It is calculated as TC = [REFOUT/REFOUT] / T. Note 10: See Figure 2. Note 11: Defined as the change in positive full scale caused by a 5% variation in the nominal supply voltage. Tested with one input at full scale and all others at AGND. VREFIN = 2.5V (internal). Note 12: Tested with VIN = AGND on all channels, VREFIN = 2.5V (internal). Note 13: The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load. Note 14: The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF capacitor. Thus, the time given is the part's true bus-relinquish time, independent of the external bus loading capacitance.
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
______________________________________________________________Pin Description
PIN 1, 2 3, 4 5 6 7 8, 36 9-16 17 18 19, 20 21-24 25 26 27 28 29 30 31 32, 33 34, 35 NAME CH2B, CH2A CH1B, CH1A AVDD REFIN REFOUT AGND D13-D6 DVDD DGND D5, D4 D3/A3-D0/A0 CLK CS WR RD CONVST INT AVSS CH4A, CH4B CH3A, CH3B FUNCTION Channel 2 Multiplexed Inputs, single-ended Channel 1 Multiplexed Inputs, single-ended +5V 5% Analog Supply Voltage External Reference Input/Internal Reference Output. Bypass with a 0.1F capacitor to AGND. Reference-Buffer Output. Bypass with a 4.7F capacitor to AGND. Analog Ground. Both pins must be tied to ground. Data Bits. D13 = MSB. +5V 5% Digital Supply Voltage Digital Ground Data Bits Bidirectional Data Bits/Address Bits. D0/A0 = LSB. Clock Input (duty cycle must be 30% to 70%). Chip-Select Input (active-low) Write Input (active-low) Read Input (active-low) Conversion-Start Input. Rising edge initiates sampling and conversion sequence. Interrupt Output. Falling edge indicates the end of a conversion sequence. -5V 5% Analog Supply Voltage Channel 4 Multiplexed Inputs, single-ended Channel 3 Multiplexed Inputs, single-ended
_______________Detailed Description
The MAX125/MAX126 use a successive-approximation conversion technique and four simultaneous-sampling track/hold (T/H) amplifiers to convert analog signals into 14-bit digital outputs. Each T/H has two multiplexed inputs, allowing a total of eight inputs. Each T/H output is converted and stored in memory to be accessed sequentially by the parallel interface with successive read cycles. The MAX125/MAX126 internal microsequencer can be programmed to digitize one, two, three, or four inputs sampled simultaneously from either of the two banks of four inputs (see Figure 2). The conversion timing and control sequences are derived from a 16MHz external clock, the CONVST
1.6mA
TO OUTPUT PIN 120pF
1.6V
1.0mA
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
REFIN AGND REFOUT
BANDGAP REFERENCE 10k CH1A A CH1B B MUX T/H 2.50V
CH2A
A B
MUX
T/H VREF MUX
CH2B
CH3A A B CH3B MUX T/H
COMP
CH4A A CH4B B MUX T/H
14-BIT DAC
SAR
VREF
14x4 RAM D0/A0 (LSB) AVDD D1/A1 AGND THREE-STATE OUTPUT DRIVERS D2/A2 D3/A3
AVSS
CONTROL LOGIC
D13 (MSB)
MAX125 MAX126
BUS INTERFACE
CLK
CONVST
INT
CS
RD
WR
DVDD
DGND
Figure 2. Functional Diagram
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
HOLD C HOLD 7pF FROM MICROSEQUENCER
BUFFER CH_A 5k S1A C IN 5k S3A S2A
HOLD
TRACK
TRACK
MUX
CH_B
5k
S1B
S2B
C IN
5k S3B REFOUT DAC
MAX125 MAX126
SAR
Figure 3. Equivalent Input Circuit
signal, and the programmed mode. The T/H amplifiers hold the input voltages at the CONVST rising edge. Additional CONVST pulses are ignored until the last conversion for the sample is complete. The ADC converts each assigned channel in 3s and stores the result in an internal 4x14-bit memory. At the end of the last conversion, INT goes low and the T/H amplifiers begin to track the inputs again. The data can be accessed by applying successive pulses to the RD pin. Successive reads access data words sequentially. The memory is not random-access; data from CH1 is always read first. After accessing all programmed channels, the address pointer selects CH1 again. Additional read pulses cycle through the data words. CS can be held low during successive reads. The T/H's input tracking circuitry has an 8MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid highfrequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
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The MAX125's input range is 5V, and the MAX126's input range is 2.5V. The input resistance for both parts is 10k. An input protection structure allows input voltages to 17V without harming the IC. This protection is also active in shutdown mode. The MAX125/MAX126 feature four simultaneous T/Hs. Each T/H has two multiplexed inputs. A T-switch input configuration provides excellent hold-mode isolation. Allow 1s acquisition time for 14-bit accuracy. The T/H aperture delay is typically 10ns. The 500ps aperture-delay mismatch between the T/Hs allows the relative phase information of up to four different inputs to be preserved. Figure 3 shows the equivalent input circuit, illustrating the ADC's sampling architecture. Only one of four T/H stages with its two multiplexed inputs (CH_A and CH_B) is shown. All switches are in track configuration for channel A. An internal buffer charges the hold capacitor to minimize the required acquisition time between conversions. The analog input appears as a 10k resistor in parallel with a 16pF capacitor.
Analog Input Range and Input Protection
Track/Holds
Input Bandwidth
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
tCW CONVST tCONV INT tCWS CS tCRS RD tRD t WR WR tDA tDH DATA tAS tAH DATA IN CH1 CH2 CH3 CH4 t RD tCRH tCWH tCSD tID tACQ
Figure 4. Timing Diagram
CS
RD inputs and forces the interface into a high-Z state. Figure 4 details the interface timing. The MAX125/MAX126 have eight conversion modes plus power-down, which are programmed through a bidirectional parallel interface. At power-up, the devices default to the mode Input Mux A/Single-Channel Conversion. The user can select between two banks (mux inputs A or mux inputs B) of four simultaneoussampled input channels, as illustrated in Figure 2. An internal microsequencer can be programmed to convert one, two, three, or four channels of the selected bank per sample. For a single-channel conversion, CH1 is digitized, and then INT goes low to indicate completion of the conversion. For multichannel conversions, INT goes low after the last channel has been digitized. To input data into the MAX125/MAX126, pull CS low, program the bidirectional pins A0-A3 (Table 1), and pulse WR low. Data is latched into the devices on the WR or CS rising edge. The ADC is now ready to convert. Once programmed, the ADCs continue operating in the same mode until they are reprogrammed or until power is removed. Figure 5 shows an example of programming a four-channel conversion using Input Mux A.
Programming Modes
WR
A0 (LSB) A1
A2
A3
Figure 5. Programming a Four-Channel Conversion, Input Mux A
Between conversions, the buffer input is connected to channel 1 of the selected track/hold bank. When a channel is not selected, switches S1, S2, and S3 are placed in hold mode to improve channel-to-channel isolation. Input data (A0-A3) and output data (D0-D13) are multiplexed on a three-state bidirectional interface. This parallel I/O can easily be interfaced with a microprocessor (P) or DSP. CS, WR, and RD control the write and read operations. CS is the standard chip-select signal, which enables the controller to address the MAX125/MAX126 as an I/O port. When CS is high, it disables the WR and
Digital Interface
Starting a Conversion After programming the MAX125/MAX126 as outlined in the Programming Modes section, pulse CONVST low to initiate a conversion sequence. The analog inputs are sampled at the CONVST rising edge. Do not start a new conversion while the conversion is in progress. Monitor the INT output. A falling edge indicates the end of a conversion sequence.
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
Table 1. Modes of Operation
A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 X A1 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X CONVERSION TIME (s) 3 6 9 12 3 6 9 12 -- MODE Input Mux A/Single-Channel Conversion (default at power-up) Input Mux A/Two-Channel Conversion Input Mux A/Three-Channel Conversion Input Mux A/Four-Channel Conversion Input Mux B/Single-Channel Conversion Input Mux B/Two-Channel Conversion Input Mux B/Three-Channel Conversion Input Mux B/Four-Channel Conversion Power-Down
X = Don't care
TO DAC
REFOUT
7
(2.5V)
4.7F AV = 1 REFIN 6 (2.5V)
address pointer is reset to CH_1. For multichannel conversions, up to four RD falling edges sequentially access the data for channels 1 through 4. For n channels converted (1 < n 4), the address pointer is reset to CH_1 after n RD pulses. Do not perform a read operation during conversion, as it will corrupt the conversion's accuracy.
__________Applications Information
0.1F 10k
MAX125 MAX126
The MAX125/MAX126 require a TTL-compatible clock up to 16MHz for proper operation. The clock duty cycle's range is between 30% and 70%. The MAX125/MAX126 can be used with an internal or external reference voltage. An external reference can be connected directly at REFIN. An internal buffer with a gain of +1 provides 2.5V at REFOUT.
External Clock
Internal and External Reference
2.5V
Figure 6. Internal Reference
Reading a Conversion Digitized data from up to four channels are stored in memory to be read out through the parallel interface. After receiving an INT signal, the user can access up to four conversion results by performing up to four read operations. With CS low, the conversion result from CH_1 is accessed, and INT is reset high on the first RD falling edge. On the RD rising edge, the internal address pointer is advanced. If a single conversion is programmed, only one RD pulse is required, and the
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Internal Reference The full-scale range with the internal reference is 5V for the MAX125 and 2.5V for the MAX126. Bypass REFIN with a 0.1F capacitor to AGND and bypass the REFOUT pin with a 4.7F (min) capacitor to AGND (Figure 6). The maximum value to compensate the reference buffer is 22F. Larger values are acceptable if low-ESR capacitors are used. External Reference For operation over a wide temperature range, an external 2.5V reference with tighter specifications improves accuracy. The MAX6325 is an excellent choice to match the MAX125/MAX126 accuracy over the commercial and extended temperature ranges with a
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
OUTPUT CODE
TO DAC
REFOUT
7
(2.5V)
011 . . . 111 011 . . . 110
4.7F
000 . . . 010
AV = 1
000 . . . 001
1LSB =
MAX125 MAX126
REFIN
6
(2.5V) OUT
000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
4VREFOUT 16384
MAX6325
10k
100 . . . 001 100 . . . 000
2.5V
- FS FS = 2 x VREFOUT (MAX125) FS = VREFOUT (MAX126) ZERO INPUT VOLTAGE (LSB) +FS - 1LSB
Figure 7. External Reference
Figure 8. Bipolar Transfer Function
1ppm/C (max) temperature drift. Connect an external reference at REFIN as shown in Figure 7. The minimum impedance is 7k for DC currents in both normal operation and shutdown. Bypass REFOUT with a 4.7F lowESR capacitor. When power is first applied, the internal power-on-reset circuitry activates the MAX125/MAX126 with INT = high, ready to convert. The default conversion mode is Input Mux A/Single-Channel Conversion. See the Programming Modes section if other configurations are desired. After the power supplies have been stabilized, the reset time is 5s; no conversions should be performed during this phase. At power-up, data in memory is undefined. Software power-down is activated by setting bit A3 of the control word high (Table 1). It is asserted after the WR or CS rising edge, at which point the ADC immediately powers down to a low quiescent-current state. AVDD drops to less than 1.5mA, and AVSS is reduced to less than 1mA. The ADC blocks and reference buffer are turned off, but the digital interface and the reference remain active for fast power-up recovery. Wake up the MAX125/MAX126 by writing a control word (A0-A3, Table 1). The bidirectional interface interprets a logic zero at A3 as the start signal and powers up in the mode selected by A0, A1, and A2. The reference
buffer's settling time and the bypass capacitor's value dominate the power-up delay. With the recommended 4.7F at REFOUT, the power-up delay is typically 5s. The MAX125/MAX126 have bipolar input ranges. Figure 8 shows the bipolar/output transfer function. Code transitions occur at successive-integer least significant bit (LSB) values. Output coding is twos-complement binary with 1LSB = 610V for the MAX125 and 1LSB = 305V for the MAX126. An output demultiplexer circuit is useful for isolating data from one channel in a four-channel conversion sequence. Figure 9's circuit uses the external 16MHz clock and the INT signal to generate four RD pulses and a latch clock to save data from the desired channel. CS must be low during the four RD pulses. The channel is selected with the binary coding of two switches. A 16-bit 16373 latch simplifies layout. Vector motor control requires monitoring of the individual phase currents. In their most basic application, the MAX125/MAX126 simultaneously sample two currents (CH1A and CH2A, Figure 10) and preserve the necessary relative phase information. Only two of the three phase currents have to be digitized, because the third component can be mathematically derived with a coordinate transformation.
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Transfer Function
Power-On Reset
Output Demultiplexer
Software Power-Down
Motor-Control Applications
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
VCC VCC 1/2 HC74 PRE D CLR VCC A B C D (LSB) 0 1 2 3 RCO P0 P1 P2 P3 P4 EXTERNAL CLOCK P5 P6 P7 Q Q CLR ENP ENT LOAD HC688 HC161 RD
INT
P=Q
VCC
Q0 Q1 Q2 Q3 10k Q4 Q5 Q6 Q7 G CH1 CH2 CH3 CH4 0 1 0 1 0 0 1 1 EXTERNAL CLOCK
LATCH CLOCK (TO 16373 LATCH)
Figure 9. Output Demultiplexer Circuit
The circuit of Figure 10 shows a typical vector motorcontrol application using all available inputs of the MAX125/MAX126. CH1A and CH2A are connected to two isolated Hall-effect current sensors and are a part of the current (torque) feedback loop. The MAX125/MAX126 digitize the currents and deliver raw data to the following DSP and controller stages, where the vector processing takes place. Sensorless vector control uses a computer model for the motor and an algorithm to split each output current into its magnetizing (stator current) and torque-producing (rotor current) components.
If a 2- to 3-phase conversion is not practical, three currents can be sampled simultaneously with the addition of a third sensor (not shown). Optional voltage (position) feedback can be derived by measuring two phase voltages (CH3A, CH4A). Typically, an isolated differential amplifier is used between the motor and the MAX125/MAX126. Again, the third phase voltage can be derived from the magnitude (phase voltage) and its relative phase. For optimum speed control and good load regulation close to zero speed, additional velocity and position feedback are derived from an encoder or resolver and
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
MAIN DC RESOLVER/ ENCODER EXTERNAL SETPOINTS CONTROLLER POWER STAGE AC AC MOTOR MOTOR R/E
BUFFER
14 SIMULTANEOUS T/H
CH1
B A
AUX
DSP
MAX125 MAX126
CH2
B A
MAIN DC
14 BIT ADC + MICROSEQUENCER
CH3
B A
TEMP VELOCITY FEEDBACK
CH4
B
C
Figure 10. Vector Motor Control
brought to the MAX125/MAX126 at CH4B. The additional channels can be used to evaluate slower analog inputs, such as the main DC bus voltage (CH2B), temperature sensors (CH3B), or other analog inputs (AUX, CH1B).
For optimum system performance, use printed circuit boards with separate analog and digital ground planes. Wire-wrapped boards are not recommended. Connect the two ground planes together at the lowimpedance power-supply source. Connect DGND and AGND together at the IC. For the best ground connection, connect the DGND and AGND pins together and
Power-Supply Bypassing and Ground Management
connect that point to the system analog ground plane to avoid interference from other digital noise sources. If DGND is connected to the system digital ground, digital noise may get through to the ADC's analog portion. The AGND pins must be connected directly to a lowimpedance ground plane. Extra impedance between the pins and the ground plane increases crosstalk and degrades INL. Bypass AVDD and AVSS with 0.1F ceramic capacitors to AGND. Mount them with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Bypass DVDD with a 0.1F ceramic capacitor to DGND.
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VOLTAGE/POSITION FEEDBACK
A
CURRENT/TORQUE FEEDBACK
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS MAX125/MAX126
__________________Pin Configuration
TOP VIEW
CH1A CH1B CH2A CH2B CH3A CH3B CH4A CH4B +5V 0.1F AGND 0.1F -5V 0.1F 0.1F REFOUT 4.7F CLK CONVST INT CS RD WR DGND AVSS REFIN AVDD
__________Typical Operating Circuit
CH2B 1 CH2A 2 CH1B 3 CH1A 4 AVDD 5
36 AGND 35 CH3B 34 CH3A 33 CH4B 32 CH4A
REFIN 6 REFOUT 7 AGND 8 D13 (MSB) 9 D12 10 D11 11 D10 12 D9 13 D8 14 D7 15 D6 16 DVDD 17 DGND 18
MAX125 MAX126
31 AVSS 30 INT 29 CONVST 28 RD 27 WR 26 CS 25 CLK 24 D0/A0 (LSB) 23 D1/A1 22 D2/A2 21 D3/A3 20 D4 19 D5 16MHz
MAX125 MAX126
D0/A0 D1/A1 D2/A2 D3/A3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 DVDD +5V
SSOP
CONTROL INTERFACE
___________________Chip Information
TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED TO AVSS
PACKAGE TYPE 36 SSOP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE A36-4 DOCUMENT NO. 21-0040
14
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2x4-Channel, Simultaneous-Sampling 14-Bit DAS
Revision History
REVISION NUMBER 2 3 REVISION DATE 6/07 7/08 DESCRIPTION Updated Ordering Information section Added line to DC Accuracy section of EC table PAGES CHANGED 1, 2, 15 2
MAX125/MAX126
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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